1. Field of the Invention
This invention relates to a semiconductor integrated circuit for controlling a power source for use such that the semiconductor integrated circuit is mounted on a memory card which has a primary battery and/or a second battery serving as backup power sources for a RAM of the memory card.
More particularly, the present invention relates to a semiconductor integrated circuit for controlling a power source such that if the semiconductor integrated circuit has detected drop or interruption of power source potential that is supplied from a terminal unit on a system to a memory card, then it switches the power supply from the terminal unit on the system to a backup power source and, if it has detected drop of the power source potential of the primary battery, then it transmits an alarm signal for urging the primary battery to be changed.
2. Description of the Related Art
Initially, the usual structure of a memory card will now be described with reference to FIGS. 16, 17 and 18.
Referring to FIG. 16, a memory card 2 is electrically connected to a terminal unit 1 of a system through a connector in such a manner that the memory card 2 is connected to the terminal unit 1 of the system through a power source potential supply line 3, a ground potential line 4 and an alarm signal line 5, the memory card 2 being as well as connected to the same through data lines and the like.
The memory card 2 has a semiconductor integrated circuit 6 for controlling a power source, a storage means 7, a first backup power source 8, a second backup power source 9, a setting means 10 and a control means 11, which are mounted thereon.
Note that a memory card 2A having only the first backup power source 8 mounted thereon and a memory card 2B having only the second backup power source 9 mounted thereon as shown in FIGS. 17 and 18 have been used. Therefore, memory cards are classified into three types on the basis of the state where the backup power source is mounted. It should be noted that the memory cards respectively are structured into the types that are adaptable to rated power source potentials of the terminal unit 1 of the system, as will be described later.
In case where the memory card 2 is connected to the terminal unit 1 of the system through the connector, the semiconductor integrated circuit 6 for controlling a power source usually supplies, to the memory card 2, power supplied from the terminal unit 1 of the system through the power source potential supply line 3.
If the foregoing integrated circuit 6 has detected drop or interruption of the power source potential supplied from the terminal unit 1 of the system, the integrated circuit 6 switches supply of the power to be used in the memory card 2 so that the power is supplied from the first backup power source 8 or the second backup power source 9. In a case where the memory card 2 has been removed from the terminal unit 1 of the system, the foregoing integrated circuit 6 similarly switches the power supply.
The foregoing integrated circuit 6 detects whether or not the power source potential of the first backup power source 8 is sufficiently high for the storage means 7 to store data. If the potential is unsatisfactorily low, the foregoing integrated circuit 6 transmits, to the terminal unit 1 of the system through the alarm signal line 5, an alarm signal for urging the first backup power source 8 to be changed.
In recent years, voltage levels of, for example, 5 V and 3 V, have been rated as the power source potential for the terminal unit 1 of the system and, thus, two types of memory cards have been required. The semiconductor integrated circuit 6 for controlling a power source has a structure adaptable to the two types. Furthermore, the semiconductor integrated circuit 6 for controlling a power source is made to be adaptable to the memory card 2 having the first and second backup power sources 8 and 9 mounted thereon and also to the memory cards 2A and 2B each having only either of the same. Therefore, the foregoing integrated circuit 6 can be adapted to a total of six kinds of memory cards.
The storage means 7 comprises, for example, a RAM, which requires backup of a power source. If the rated power source potential of the terminal unit 1 of the system is 5 V, a RAM, the operation of which is guaranteed at 4.5 V to 5.5 V, has been used. If the rated value is 3 V, a RAM, the operation of which is guaranteed at 2.7 V to 3.3 V has been used. In a case where only storage of data is performed, a RAM requiring only about 2 V of a power source has been used.
The first backup power source 8 comprises a primary battery, such as a button-shape battery, the power source potential of which is, for example, 3 V and to which electric power cannot be charged.
The second backup power source 9 comprises a second battery, the power source potential of which is, for example 3 V and to which electric power can be supplied. When the power source potential has been lowered, the second battery is charged with electric power from the power source of the terminal unit 1 of the system supplied through the power source potential supply line 3 by means of a circuit (not shown).
The setting means 10 sets the memory card to be adaptable to the rated value of the power source potential of the terminal unit 1 of the system of 5 V or 3 V. When the semiconductor integrated circuit 6 for controlling a power source is mounted on the memory card, the setting means sets the rated value to which the memory card is adapted.
The control means 11 sets the memory card to be adaptable to the state where the backup power source is mounted such that the memory card is adapted to either one of the first and second backup power sources 8 and 9, or both the first and second backup power sources 8 and 9. When the semiconductor integrated circuit 6 for controlling a power source is mounted on the memory card, the control means sets the memory card to the selected state.
Then, the operation of the foregoing integrated circuit 6 will now be described. First, the operation to be performed when the memory card 2 is connected to the terminal unit 1 of the system will now be described. The semiconductor integrated circuit 6 for controlling a power source is supplied with the power source potential of the terminal unit 1 of the system supplied through the power source potential supply line 3. If the supplied power source potential is a predetermined rated value, the semiconductor integrated circuit 6 for controlling a power source supplies the foregoing power source potential to the circuit in the memory card 2 including the storage means 7. The memory card 2, which is operated with the power source potential of the terminal unit 1 of the system, writes data transferred from the terminal unit 1 of the system and transfers data read from storage means 7 to the terminal unit 1 of the system.
If the power source potential supplied from the terminal unit 1 of the system is lower than the rated value or if the memory card 2 has been removed from the terminal unit 1 of the system, the foregoing integrated circuit 6 detects the foregoing state and switches the supply of the power source potential from the terminal unit 1 of the system to the supply of the power source potential from the first or second backup power sources 8 or 9 to supply the power source potential to the storage means 7. Since the power source potentials of the first and second backup power sources 8 and 9 have smaller power source capacity as compared with the power source potential of the terminal unit 1 of the system, the power source potential is used only to store data of the storage means 7.
The conventional semiconductor integrated circuit for controlling a power source will now be described specifically with reference to FIGS. 19-21.
Referring to FIG. 19, reference numeral 6a represents an external power source potential node connected to the power source potential supply line 3 through the connector and serving as a system-side power source potential node, 6b represents an internal power source potential node for supplying the internal power source potential to the internal circuit of the memory card 2 including the storage means 7, 6c represents an alarm signal output node connected to the alarm signal line 5 though a connector, 6d represents a first backup power source potential node which is supplied with a first backup power source potential from the first backup power source 8, 6e represents a second backup power source potential node supplied with a second backup power source potential from the second backup power source 9, 6f represents a setting node for receiving a setting signal from the setting means 10 and 6g represents a control node for receiving a control signal from the control means
The foregoing integrated circuit 6 comprises a power source potential discriminating means (circuit) 61, a power source switching means (circuit) 62 and an alarm signal generating means (circuit) 63.
The power source potential discriminating means 61 transmits a switching signal for discriminating whether the external power source potential to be supplied to the external power source potential node 6a or the first or second backup power source potential to be supplied to the first backup power source potential node 6d or the second backup power source potential node 6e is used. That is, the power source potential discriminating means 61 detects whether the memory card 2 is connected to the terminal unit 1 of the system and whether the power source potential supplied from the terminal unit 1 of the system is the rated value in a case where the memory card 2 is connected to the terminal unit 1 of the system. In a case where the memory card 2 is not connected to the terminal unit 1 of the system and in a case where the power source potential of the terminal unit 1 of the system is lower than the rated value, the power source potential discriminating means 61 transmits the switching signal upon which the backup power sources 8 and 9 are used. In a case where the power source potential of the terminal unit 1 of the system is the rated value, the power source potential discriminating means 61 transmits the switching signal upon which the power source potential of the terminal unit 1 of the system is used.
The power source potential discriminating means 61 is in series connected between the external power source potential node 6a and the ground potential node and comprises a potential generating means, a reference potential generating means 61e and a comparison means 61d. The potential generating means comprises resistors 61a and 61b and as well as having a connection node 61c connected to the setting node 6f. The comparison means 61d is operated with the power source potential of the terminal unit 1 of the system supplied through the power source potential supply line 3, the comparison means 61d having an input node connected to the connection node 61c and another input node that receives a reference potential from the reference potential generating means 61e. The comparison means 61d transmits a switching signal upon which the external power source potential is used if the potential appeared at the connection node 61c is higher than the reference potential, the comparison means 61d transmitting a switching signal upon which the backup power source potential is used if the foregoing potential is lower than the reference potential. In this example, if the potential appeared at the connection node 61c is higher than the reference potential, then the level of the switching signal is high. If the foregoing potential is lower than the reference potential, the level of the switching signal is low.
Note that the reference potential generating means 61e, as shown in FIG. 20, comprises a constant electric current source I1 connected between the power source potential node (the external power source potential node 6a in this example) and an output node 01 (Output 1), an npn bipolar transistor Tr1 having a collector and a base connected to the output node 01 and acting as a diode device, and a resistor R1 connected between the emitter the transistor Tr1 and the ground node. The reference potential generating means 61e has a small number of circuit elements and as well as causes the reference potential appearing at the output node 01 to be stable against change in the power source potential (even if the voltage level is 5 V or 3 V) supplied to the power source potential node and the temperature.
Examples of the resistors 61a and 61b of the potential generating means and the reference potential generating means 61e of the power source potential discriminating means 61 are as follows.
The reference potential generating means 61e is enabled to generate the reference potential of 1.35 V by determining the circuit constants of the constant electric current source I1, the transistor Tr1 and the resistor R1.
The resistors 61a and 61b of the potential generating means have the same resistance value of, for example, 600 K.OMEGA. in order to cause a voltage level of 1.35 V to appear at the connection node 61c when the power source potential of the terminal unit 1 of the system supplied to the external power source potential node 6a is 2.7 V under condition that the setting node 6f is electrically floating, that is, the switching means 10a of the setting means 10 is opened in a case where the storage means 7, the operation of which is guaranteed in a power source potential range from 2.7 V to 3.3 V, is used (in a case where the memory card is adapted to the rated value of the power source potential the terminal unit 1 of the system of 3 V).
It should be noted that the setting means 10 according to this example is in series connected between the setting node 6f and the ground node and comprises the switching means 10a and a resistor 10b. When the rated power source potential of the terminal unit 1 of the system is 3 V, the switching means 10a is opened. When the rated power source potential is 5 V, the switching means 10a is closed. The resistor 10b, together with the resistors and 61b of the potential generating means, acts to generate a potential at the connection node 61c in a case where the storage means 7, the operation of which is guaranteed in a power source potential range from 4.5 V to 5.5 V, is used. The resistance value of the resistor 10b is 450 k.OMEGA. when each of the resistors 61a and 61b has the resistance value of 600 k.OMEGA. in order to cause a voltage level of 1.35 V to appear at the connection node 61c in a case where the power source potential of the terminal unit 1 of the system supplied to the external power source potential node 6a is 4.5 V.
The power source switching means 62 receives the power source potential of the terminal unit 1 of the system supplied to the external power source potential node 6a and those of the first and second backup power sources 8 and 9. Furthermore, the power source switching means 62 receives the switching signal from the power source potential discriminating means 61 and the control signal from the control means 11. In response to the switching signal, the power source switching means 62 selects the power source potential of the terminal unit 1 of the system or the power source potentials of the first and second backup power sources 8 and 9 to transmit the selected power source potential to the internal power source potential node 6b.
The power source switching means 62 is connected between the external power source potential node 6a and the internal power source potential node 6b. The power source switching means 62 comprises a P-channel MOS transistor 62a, an invertor means (an inverting circuit) 62b, a logical operating means 62c, a P-channel MOS transistor 62d, a P-channel MOS transistor 62e and a bypass means 62f.
The transistor 62a has a backgate connected to the internal power source potential node 6b so that conduction of the transistor 62a is controlled in response to the switching signal. The invertor means 62b is operated with the power source potentials of the first and second backup power sources 8 and 9. The invertor means 62b has an input node, which receives the switching signal, and an output node which is connected to the transistor 62a. The logical operating means 62c is operated with the power source potentials of the first and second backup power sources 8 and 9. The logical operating means 62c has an input node that receives the switching signal and another input node that is connected to the control node 6g. Thus, the logical operating means 62c transmits a control signal upon which whether or not the first backup power source 8 is connected to the internal power source potential node 6b is determined.
The transistor 62d is connected between the first backup power source potential node 6d and the internal power source potential node 6b. The P-channel MOS transistor 62d has a backgate connected to the internal power source potential node 6b and a gate electrode that receives the control signal from the logical operating means 62c. Thus, conduction of the transistor 62d is controlled in response to the control signal. The transistor 62e is connected between the second backup power source potential node 6e and the internal power source potential node 6d. The transistor 62e has a backgate connected to the internal power source potential node 6b and a gate electrode which receives the switching signal. In response to the switching signal, conduction of the transistor 62e is controlled. The bypass means 62f comprises a diode device 62f1 and a resistor 62f2 in series connected between the first backup power source potential node 6d and the internal power source potential node 6b. The anode electrode of the diode device 62f1 is connected to the first backup power source potential node 6d.
The logical operating means 62c comprises, for example, an OR circuit. When a high level potential (that is, the memory card 2 having the first and second backup power sources 8 and 9 mounted thereon or the memory card 2B having only the second backup power source 9 mounted thereon is loaded) is supplied to the control node 6g, the logical operating means 62c transmits a high-level control signal regardless of the level of the switching signal. When a low level potential (the memory card 2A having only the first backup power source 8 mounted thereon is loaded) is supplied to the control node 6g, the logical operating means 62c transmits a high-level control signal if the switching signal is high level and transmits a low-level control signal if the switching signal is low level.
When the gate electrode of the transistor 62d receives a low level signal, the transistor 62d is brought to a conductive state. When the same receives a high level signal, the transistor 62d acts as a diode device (in this example, the forward voltage (the threshold) is 0.6 V), the forward direction of which is arranged from the first backup power source potential node 6d to the internal power source potential node 6b, because the backgate of the transistor 62d is connected to the internal power source potential node 6b.
When the gate electrode of the transistor 62e receives a low level potential, the transistor 62e is brought to a conductive state. When the same receives a high level potential, the transistor 62d acts as a diode device (in this example, the forward voltage (the threshold) is 0.6 V), the forward direction of which is arranged from the second backup power source potential node 6e to the internal power source potential node 6b, because the backgate of the transistor 62d is connected to the internal power source potential node 6b.
The control means 11, in this example, comprises a control node 6g and a switching means 11a which establishes the electrical connection between the control node 6g and the power source potential node (which is the internal power source potential node 6b in this example) or the ground node.
The alarm signal generating means 63 comprises a reference potential generating means 63a for generating the reference potential and a comparison means 63b. The alarm signal generating means 63 discriminates whether or not the power source potential of the first backup power source 8 is sufficiently high (a predetermined potential, for example, about 2 V) for the storage means 7 to store data. If the power source potential of the first backup power source 8 is lower than the predetermined potential, the alarm signal generating means 63 transmits an alarm signal for urging change of the first backup power source 8 to the terminal unit 1 of the system through the alarm signal line 5. The comparison means 63b is operated with the power source potential of the terminal unit 1 of the system supplied to the external power source potential node 6a. The comparison means 63b has an input node which is connected to the first backup power source potential node 6d and another input node which receives the reference potential from the reference potential generating means 63a, the comparison means 63b further having an output node connected to the alarm signal output node 6c.
Note that the reference potential generating means 63a, as shown in FIG. 21, comprises a constant electric current source I2 connected between the power source potential node (the external power source potential node 6a in this example) and an output node 02 (Output 2), an npn bipolar transistor Tr2 having a collector and a base connected to the output node 02 and acting as a diode device, an npn bipolar transistor tr3 having a collector and a base connected to the emitter of the transistor tr2 and acting as a diode device, and a resistor R2 connected between the emitter of the transistor Tr3 and the ground node. The reference potential generating means 63a has a small number of circuit elements and as well as causes the reference potential appearing at the output node 02 to be stable against change in the power source potential (even if the voltage level is 5 V or 3 V) supplied to the power source potential node and the temperature.
Specifically, the reference potential generating means 63a is enabled to generate the reference potential of, for example, 2.6 V, by determining the circuit constants of the constant electric current source I2, the transistors Tr2 and Tr3 and the resistor R2.
The operation of the semiconductor integrated circuit 6 for controlling a power source will now be described. First, the foregoing integrated circuit 6 adaptable to the memory card 2 adapted to the rated power source potential of the terminal unit 1 of the system of 3 V and having both first and second backup power sources 8 and 9 will now be described.
The foregoing memory card 2 comprises the storage means 7 comprising a RAM, the operation of which is guaranteed at 2.7 V to 3.3 V. The switching means 10a of the setting means 10 is opened, and the switching means 11a of the control means 11 establishes the electrical connection between the internal power source potential node 6b and the control node 6g.
When the memory card 2 is connected to the terminal unit 1 of the system in the foregoing state, the power source potential of the terminal unit 1 of the system is supplied to the external power source potential node 6a through the power source potential supply line 3.
As a result, the potential on the basis of the power source potential of the terminal unit 1 of the system appeared at the external power source potential node 6a, that is, the potential, which has been resistance-divided by the resistors 61a and 61b of the potential generating means, appears at the connection node 61c. The potential of the connection node 61c and the reference potential (which is 1.35 V in this example) of the reference potential generating means 61e are subjected to a comparison by the comparison means 61d. If the potential of the connection node 61c is higher than the reference potential, a high-level switching signal indicating that the power source potential of the terminal unit 1 of the system is used as the internal power source potential is transmitted.
The high-level switching signal is inverted by the invertor means 62b so that a low level potential is supplied to the transistor 62a. Since the transistor 62a that has received the low level at the gate electrode thereof is brought to the conductive state, the power source potential of the terminal unit 1 of the system appeared at the external power source potential node 6a appears at the internal power source potential node 6b through the transistor 62a. Thus, the power source potential of the terminal unit 1 of the system is supplied to the internal circuit of the memory card 2 including the storage means 7.
The memory card 2, which is operated with the power source potential of the terminal unit 1 of the system, writes data transferred from the terminal unit I of the system on the storage means 7 or transfers data read from the storage means 7 to the terminal unit 1 of the system.
The high-level switching signal is also supplied to the gate electrode of the transistor 62e so that the transistor function of the transistor 62e is brought to a non-conductive state.
Therefore, the power source potential is not supplied from the second backup power source 9 to the internal power source potential node 6b so far as the potential of the internal power source potential node 6b is higher than a value obtained by subtracting the threshold for the transistor 62e to serve as a diode device from the power source potential of the second backup power source 9. Since the comparison means 61d has discriminated that the power source potential of the terminal unit 1 of the system is 2.7 V or higher and thus the power source potential of the terminal unit 1 of the system is supplied to the internal power source potential node 6b, the power source potential of the internal power source potential node 6b is 2.7 V or higher. Therefore, the power source potential is not supplied from the second backup power source 9 to the internal power source potential node 6b.
Since a high-level control signal is supplied from the control means 11 to one input node of the logical operating means 62c, a high-level control signal is transmitted from the logical operating means 62c regardless of the level of the switching signal. The high-level control signal is supplied to the gate electrode of the transistor 62d so that the transistor function of the transistor 62d is brought to s non-conductive state.
Therefore, the power source potential is not supplied from the first backup power source 8 to the internal power source potential node 6b so far as the potential of the internal power source potential node 6b is higher than a value obtained by subtracting the threshold for the transistor 62d to serve as a diode device from the power source potential of the first backup power source 8. Since the comparison means 61d has discriminated that the power source potential of the terminal unit 1 of the system is 2.7 V or higher and thus the power source potential of the terminal unit 1 of the system is supplied to the internal power source potential node 6b, the power source potential of the internal power source potential node 6b is 2.7 V or higher. Therefore, the power source potential is not supplied from the first backup power source 8 to the internal power source potential node 6b through the transistor 62d.
Furthermore, since the power source potential of the internal power source potential node 6b is higher than the value obtained by subtracting the threshold of the diode 62f1 from the first backup power source 8, no electric power is supplied from the first backup power source 8 to the internal power source potential node 6b through the bypass means 62f.
Furthermore, the comparison means 63b of the alarm signal generating means 63 subjects the power source potential of the first backup power source 8 and the reference potential (which is 2.6 V in this example) of the reference potential generating means 63a to a comparison. If the power source potential of the first backup power source 8 is lower than the reference potential, the comparison means 63b transmits an alarm signal for instructing the change of the first backup power source 8 to the terminal unit 1 of the system through the alarm signal line 5.
If the power source potential of the terminal unit of the system has been made lower than 2.7 V due to some reason during use under the foregoing condition, the potential of the connection node 61c of the power source potential discriminating means 61 is made lower than the reference potential (which is 1.35 V in this example) of the reference potential generating means 61e. Thus, the comparison means 61d transmits a low-level switching signal indicating that the backup power source is used as the internal power source potential.
The low-level switching signal is inverted by the invertor means 62b so that a high-level signal is supplied to the transistor 62a. The transistor function of transistor 62a that has received the high-level signal at the gate electrode thereof is brought into a non-conductive state. Since the power source potential of the terminal unit 1 of the system is lower than 2.7 V, supply and receipt of data between the memory card 2 and the terminal unit 1 of the system are inhibited.
The low-level switching signal is also supplied to the gate electrode of the transistor 62e so that the transistor 62e is brought to a conductive state.
Therefore, the second backup power source 9 and the internal power source potential node 6b are brought to an electrically conductive state. Thus, the power source potential can be supplied from the second backup power source 9 to the internal power source potential node 6b so that the power source potential of the internal power source potential node 6b is supplied from the second backup power source 9.
As a result, the storage means 7 is supplied with the power source potential from the second backup power source 9, and thus an undesirable loss of data stored in the storage means 7 can be prevented.
Since the transistor 62d has received the high-level control signal from the logical operating means 62c, the transistor function of the transistor 62d is in a non-conductive state. Therefore, the power source potential is not supplied from the first backup power source 8 to the internal power source potential node 6b so far as the power source potential of the internal power source potential node 6b is higher than the value obtained by subtracting the threshold for the diode function of the transistor 62d from the first backup power source 8.
When the supply of the power source potential to the internal power source potential node 6b is switched from the terminal unit 1 of the system to the second backup power source 9, scatter of the circuit devices taking place during manufacturing sometimes causes the transistor 62e to be brought to a conductive state after the transistor 62a has been brought to a non-conductive state.
However, the structure of this example, in which the transistors 62e and 62d act as diode devices and the bypass means 62f is provided, causes the power source potential to be supplied from the first backup power source 8 or the second backup power source 9 to the internal power source potential node 6b when the potential of the internal power source potential node 6b has been made lower than the value obtained by subtracting the threshold for the transistor 62e or 62d to serve as the diode device or the threshold of the diode device 62f7 of the bypass means 62f from the power source potential of the first backup power source 8 or the second backup power source 9. As a result, the potential of the internal power source potential node 6b cannot be made lower than a certain level. Therefore, the problem of loss of data stored in the storage means 7 can be prevented.
Then, the operation of the foregoing integrated circuit 6 adapted to the memory card 2b having only the second backup power source 9 mounted thereon will now be described.
Also in this case, the integrated circuit 6 is operated similarly to the foregoing integrated circuit 6 that is adapted to the memory card 2 having the first and second backup power sources 8 and 9 mounted thereon.
However, since the first backup power source 8 is omitted from the structure, the supply of the power source potential from the first backup power source 8 to the internal power source potential node 6b is interrupted but the power source potential is supplied from the second backup power source 9 if scatter of the circuit device taking place due to manufacturing brings the transistor 62e to a conductive state after the transistor 62a has been brought to a non-conductive state when the supply of the power source potential to the internal power source potential node 6b is switched from the terminal unit 1 of the system to the second backup power source 9. Therefore, no problem is raised.
Then, the operation of the foregoing integrated circuit 6 adapted to the memory card 2A having only the first backup power source 8 mounted thereon will now be described.
In this case, the control means 11 is set to a state where the ground potential node and the control node 6g are electrically connected by the switching means
Therefore, one of the inputs of the logical operating means 62c receives the low-level control signal. Thus, the logical operating means 62c transmits a control signal, the level of which corresponds to the level of the foregoing switching signal.
In a case where the power source potential of the terminal unit 1 of the system is sufficiently high and therefore the power source potential of the terminal unit of the system is supplied to the internal power source potential node 6b, a high-level switching signal is transmitted from the power source potential discriminating means 61. The transistor 62a that has received a low level potential at the gate electrode thereof through the invertor means 62b is brought to a conductive state. As a result, the memory card 2A, which is operated with the power source potential of the terminal unit 1 of the system, writes data transferred from the terminal unit 1 of the system or transfers data read from the storage means 7 to the terminal unit 1 of the system.
On the other hand, the logical operating means 62c, which receives the high-level switching signal at another input node thereof, transmits high level. The transistor function of the transistor 62d, which receives the high-level control signal at the gate electrode thereof, is brought to a non-conductive state. Therefore, the power source potential of the internal power source potential node 6b is not made lower than the predetermined level. Thus, the power source potential is not supplied from the first backup power source 8 to the internal power source potential node 6b through the transistor 62d and the bypass means 62f.
If the power source potential of the terminal unit of the system has been lowered due to some reason and therefore a low-level switching signal has been transmitted from the power source potential discriminating means 61, the transistor function of the transistor 62a, which has received a high level at the gate electrode thereof through the invertor means 62b, is brought into a non-conductive state. Since the power source potential of the terminal unit 1 of the system is lower than 2.7 V at this time, transfer and receipt of data between the memory card 2A and the terminal unit 1 of the system are inhibited.
On the other hand, the output from the logical operating means 62c, which receives the low-level switching signal at another input node, is low level. The transistor function of the transistor 62d, which receives the low-level control signal at the gate electrode thereof, is brought to a conductive state.
Therefore, the first backup power source 8 and the internal power source potential node 6b are made to be electrically conductive. As a result, the power source potential can be supplied from the first backup power source 8 to the internal power source potential node 6b so that the power source potential is supplied to the internal power source potential node 6b from the first backup power source 8.
As a result, the storage means 7 is supplied with the power source potential from the first backup power source 8. Therefore, the problem of loss of data stored in the storage means 7 can be prevented.
In a case where the transistor 62d is brought to a conductive state after the transistor 62a has been brought to a non-conductive state due to scatter of the circuit device caused from manufacturing when the supply of the power source potential to the internal power source potential node 6b is switched from the terminal unit 1 of the system to the first backup power source 8, the structure of this example, in which the transistor 62d serves as a diode device and the bypass means 62f is provided, causes the power source potential to be supplied from the first backup power source 8 to the internal power source potential node 6b when the potential of the internal power source potential node 6b has been made lower than the value obtained by subtracting the threshold of the transistor 62d to serve as the diode device or the threshold of the diode device 62f1 of the bypass means 62f from the power source potential of the first backup power source 8. As a result, the potential of the internal power source potential node 6b cannot be made lower than a certain level. Therefore, a problem of loss of data stored in the storage means 7 can be prevented.
The comparison means 63b of the alarm signal generating means 63 subjects the power source potential of the first backup power source 8 and the reference potential (which is 2.6 V in this case) of the reference potential generating means 63a to a comparison. If the power source potential of the first backup power source 8 is lower than the reference potential, an alarm signal for instructing change of the first backup power source 8 is transmitted to the terminal unit 1 of the system through the alarm signal line 5.
The operation of the foregoing integrated circuit 6 adaptable to the memory card 2 adapted to the rated power source potential of the terminal unit 1 of the system of 3 V and having both first and second backup power sources 8 and 9 mounted thereon will now be described, the operation being performed when the memory card 2 has been removed from the terminal unit 1 of the system.
Since the comparison means 61d of the power source potential discriminating means 61 is operated by the power source for the terminal unit 1 of the system, the output from the comparison means 61d is lowered when the memory card 2 has been removed from the terminal unit 1 of the system.
Since invertor means 62b is operated by the backup power source, the invertor means 62b receives a low level from the comparison means 61d and supplies a high level to the gate electrode of the transistor 62a so as to bring the transistor function of the transistor 62a to a non-conductive state.
The transistor 62e, which receives the low level at the gate electrode thereof, is brought to a conductive state, thus causing the power source potential of the second backup power source 9 to be supplied to the internal power source potential node 6b.
Since the control means 11 has a structure to receive the power source potential from the internal power source, the output from the control means 11 is high level even if the memory card 2 has been separated from the terminal unit 1 of the system. Therefore, the logical operating means 62c, which is operated by the backup power source, receives a high level from the control means 11 and a low level from the comparison means 61d to supply a high level to the gate electrode of the transistor 62d. Thus, the logical operating means 62c brings the transistor function of the transistor 62d to a non-conductive state. As a result, the power source potential of the first backup power source 8 is not supplied to the internal power source potential node 6b.
In short, since the power source potential is supplied from the second backup power source 9 to the internal power source potential node 6b in a case where the memory card 2 has been removed from the terminal unit 1 of the system, the problem of loss of data stored in the storage means 7 can be prevented.
Since the comparison means 63b of the alarm signal generating means 63 is supplied with the power source potential from the terminal unit 1 of the system, it does not transmit the alarm signal.
The operation of the foregoing integrated circuit 6 adapted to the memory card adaptable to a rated power source potential of the terminal unit 1 of the system of 5 V will now be described.
In this case, the storage means 7 comprises a RAM, the operation of which is guaranteed at 4.5 V to 5.5 V, and the switching means 10a of the setting means 10 is closed.
Therefore, the potential appeared at the external power source potential node 6a is resistance-divided by the parallel resistance consisting of the resistor 61a of the potential generating means of the power source potential discriminating means 61, the resistor 61b of the potential generating means and the resistor 10b of the setting means 10 so that the divided potential appears at the connection node 61c of the potential generating means. The potential appeared at the connection node 61c and the reference potential (which is 1.35 V in this example) and the reference potential of the reference potential generating means 61e are subjected to a comparison by the comparison means 61d. As a result, a switching signal, which is the result of the comparison, is transmitted. The other operations are the same as those to be performed in the case where the rated power source potential of the terminal unit 1 of the system is 3 V.
Note that the potential appearing at the connection node 61c of the potential generating means is made to be 1.35 V when the potential appeared at the external power source potential node 6a is 4.5 V by setting the resistance values of the resistors 61a and 61b of the potential generating means and the resistor 10b of the setting means 10.
However, the conventional semiconductor integrated circuit 6 for controlling a power source has the following problems.
A first problem will now be described. Since the resistor 10b of the setting means 10 is, from outside, attached individually from the foregoing integrated circuit 6, the resistance value of the attached-type resistor 10b cannot easily accurately be maintained to correspond to the resistors 61a and 61b of the power source potential discriminating means 61. Furthermore, the attached-type resistor 10b causes the degree of integration of the memory card to be lowered.
A second problem arises as follows: since the power source switching means 62 has the structure in which only one transistor 62d is connected between the internal power source potential node 6b and the first backup power source 8, supply of a high level to the gate causes the transistor 62d to serve as a diode, the forward voltage of which is 0.6 V when the power source potential of the first backup power source 8 is 3.3 V because it has been just changed in a case where the power source potential of the terminal unit 1 of the system supplied to the internal power source potential node 6b is the lowest level of 2.7 V. As a result, an electric current flows from the first backup power source 8 to the internal power source potential node 6b through the transistor 62d. The flow leads to a fact that the life of the first backup power source 8 is shortened.
Since the bypass means 62f having only one diode device 62f1 is connected between the internal power source potential node 6b and the first backup power source 8, a similar problem arises.
A third problem will now be described. The alarm signal generating means 63 has a structure that the reference potential generating means 63a is operated with the power source potential of the terminal unit 1 of the system and is composed of the constant electric current source I2, the transistors Tr2 and Tr3 and the resistor R2 that are connected in series, as shown in FIG. 21. However, since the constant electric current source I2 encounters voltage drop of 0.5 V or more, it has been very difficult to generate the reference potential of 2.6 V from the power source potential of 3 V in a case where the power source potential of the terminal unit 1 of the system is the rated value of 3 V.